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Cadence 2017招聘_上海校园招聘

2018-12-01 22:42:45
Cadence 2017招聘_上海校园招聘 [原帖] 发信人: lysh(lysh), ■ yingjiesheng.com■ 标 题: 【全职】Cadence上海 招聘高级产品/验证工程师 发信站: 饮水思源 (2017年05月25日15:37:20 星期四) 投递方式: If you have interest , PLS send your update CV to job_china@cadence.com(简历投 递格式:姓名 学校 申请职位 工作地点) 接受2017年应届硕士、博士生。 1. Lead Product Validation Engineer Position Description: 1. Identify timing sign-off challenges in complex SOC designs and the correlat ion issues between preRoute postroute in advacned process nodes. 2. Proactively provide extraction timing development suggestions to R D. 3. Build up parasitics timing analysis expertise and deliver support to fiel d team and customers whenever needed. 4. Required to acquire expertise and ownership over existing product component s as well as develop brand new product features. Position Requirements: 1. Bachelor with 5 years related experience or Master with at least 3 years re lated experience in design house, FAB or EDA company. 2. Rich experience in IC design flow (front-end or back-end). 3. Experience in advanced nodes designs or knowledge in timing closure is a st rong plus. 4. Good Unix System knowledge and script skill of TCL/TK/CSH/PERL. 5. Excellent capability of self-learning, problem solving skills. 6. Being proactive and self-motivated. 7. Strong leadership. 8. Good written English and oral English is a strong plus. Position Description: 1. Identify timing sign-off challenges in complex SOC designs and the correlat ion issues between preRoute postroute in advanced process nodes. 2. Proactively provide STA development suggestions to R D. 3. Build up extraction STA expertise and deliver support to field team and c ustomers whenever needed. 4. Required to acquire expertise and ownership over existing product component s as well as develop brand new product features. Position Requirements: 1. Bachelor with 5 years related experience or Master with at least 3 years re lated experience in design house, FAB or EDA company. 2. Rich experience in IC design flow (front-end or back-end). 3. Experience in advanced nodes designs or knowledge in timing closure is a st rong plus. 4. Good Unix System knowledge and script skill of TCL/TK/CSH/PERL. 5. Excellent capability of self-learning, problem solving skills. 6. Being proactive and self-motivated. 7. strong leadership. 8. Good written English and oral English is a strong plus. Position Description: The engineer will work on Innovus QOR validation. Monitor flow QOR in weekly basis, debug QOR issues deeply across whole implementation flow from placement to CTS and to post route optimization. Also need to debug synthesis flow depe nding on project demand. Also the engineer need to write scripts to improve ef ficiency. Position Requirements: 1. Master degree or bachelor degree with 2~3 years working experience. 2. Solid background knowledge in digital backend design. 3. Be familiar with Linux system, and scripting skills with TCL or PERL or She 4. Patient, and good responsibility. 5. Good communication in English and Chinese. Position Description: This engineer will work in Encounter block implementation product validation t eam. The responsibilities include: 1. Assist in Cadence EDI development and validation Validate and maintain comp rehensive unit and flow test cases for Encounter Digital Implementation System 2. Develop test suites of the new features of EDI functions. Position Requirements: 1. MS of EE/CS. 2. Digital IC design knowledge is necessary, statistic timing analysis knowled ge is a strong plus. 3. Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus. 4. Good communication in English and Chinese, good confidence and self-motivat Position Description: This PV engineer mainly works for advanced STA (Static Timing Analysis) and DelayCal features validation: 1. Qualify delay calculation and timing analysis result in Innovus system. 2. Maintain comprehensive regression suites for monitoring STA delayCal stab ilities. 3. Upgrading regression cases to use advanced design node data and check the i mpact. Position Requirements: 1. Master degree or bachelor degree with 2~3 years working experience. 2. Solid background knowledge in digital backend design, knowledge in STA or d elayCal is a strong plus. 3. Be familiar with Linux system, and scripting skills with TCL or PERL or She 4. Patient, and good responsibility. 5. Good communication in English and Chinese. Position Description: 1. Assist in Cadence hierarchical and DB areas developement and validation. 2. Validate and maintain comprehensive hierarchical/Database unit and flow tes t cases for Encounter Digital Impelementation System. 3. Develope testsuites of the new features of hierarchical and Database functi onal/flow solution. Position Requirements: 1. MS in EE or related majors. 2. Digital IC design knowledge is necessary, statistic timing analysis knowled ge is a strong plus. 3. Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus. 4. Good communication in English and Chinese, good confidence and self-motivat Position Description: 1. Design and develop cutting edge technologies of Encounter/Innovus, to addre ss future and immediate customer requirements 2. Collaborate with R D and production validation team to deliver high quality software release 3. Provide technical support and trainings for Cadence AP business 4. Communicate with global cross-function team to create technical solutions a nd involve in customer engagement Position Requirements: 1. CS/EE MS with 1 years IC physical design experience. 2. Be familiar with IC back-end design flow, including place, route, clock tre e synthesis and timing optimization. 3. Strong analysis/debug capability for technical issues. 4. Good team spirit and be able to work under pressure. 5. Good communication skill in English Job Description: 1. Design and develop cutting edge technologies of Encounter/Innovus, to addre ss future and immediate customer requirements. 2. Collaborate with R D and production validation team to deliver high quality software release 3. Provide technical support and trainings for Cadence AP business. 4. Communicate with global cross-function team to create technical solutions a nd involve in customer engagement. Position Requirements: 1. CS/EE MS with 3 years or PhD with 1 years IC physical design experience. 2. Be familiar with IC back-end design flow, including place, route, clock tre e synthesis and timing optimization. 3. Strong analysis/debug capability for technical issues. 4. Good team spirit and be able to work under pressure. 5. Good communication skill in English. Job Description: 1. Design and develop power planning and power routing features in Innovus, to address future and immediate customer requirements. 2. Collaborate with R D for the technical specification of new enhancements. W ork with production validation team to deliver high quality software release. 3. Provide technical support and trainings for Cadence AP business. 4. Communicate with global cross-function team to create technical solutions a nd involve in customer engagement. Position Requirements: 1. CS/EE MS with 5 years or PhD with 3 years IC physical design experience. 2. Power planning, routing or DRC fixing experience in design tape-out. 3. Be familiar with IC back-end design flow. Knowledge of LEF/DEF and advanced process node DRC rule is a plus. 4. Strong analysis/debug capability for technical issues. 5. Good team spirit and be able to work under pressure. 6. Good communication skill in English. ※ 来源:·饮水思源 bbs.sjtu.edu.cn·[FROM: 158.140.1.28] 深圳织造机械品牌大全
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